---
title: Design Verification Engineer, Silicon at Google
description: Google is hiring for the Design Verification Engineer, Silicon role in Mountain
  View, CA. See the full description and apply.
type: job
url: https://www.foundrole.com/jobs/design-verification-engineer-silicon-at-google-01a0d985-b147-7d4d-b3bd-e995c9180189
date: 2026-09-27T23:47:25Z
og_description: Join Google as Design Verification Engineer, Silicon in Mountain View, CA. Pays
  $138K–$197K per year. Requires 4+ years of experience.
og_image: https://www.foundrole.com/og/yow3to.png
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  - label: Home
    url: https://www.foundrole.com/
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---

| | |
|---|---|
| **Company** | [Google](https://www.foundrole.com/companies/google?utm_source=ai_markdown) |
| **Location** | Mountain View, CA |
| **Salary** | $138K/yr - $197K/yr |
| **Posted** | Sep 25, 2026 |
## Description

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.  

US: $138000 - $197000 (USD) + 15% bonus target + equity + benefits  

Learn more about [benefits at Google](https://www.google.com/about/careers/applications/benefits/).

- Plan verification strategies for complex digital design blocks by thoroughly understanding design specifications and collaborating with design engineers to identify critical verification scenarios.
- Build constrained-random verification environments utilizing SystemVerilog and Universal Verification Methodology (UVM).
- Define and implement comprehensive coverage metrics targeting stimulus and corner cases.
- Debug test failures alongside design engineers to ensure functionally correct design blocks.
- Achieve coverage closure to identify verification gaps and demonstrate progress toward tape-out.

### Minimum qualifications:

- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 4 years of experience working with verification methodologies and languages, including SystemVerilog and UVM.
- Experience with interconnect protocols such as AXI, APB, and ACE.
- Experience building and maintaining verification test benches, test cases, and test environments.

### Preferred qualifications:

- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience managing the full verification life cycle, from initial test planning through coverage closure.
- Expertise in advanced verification methodologies and techniques (including UVM, formal verification, and UPF-based power simulations) to ensure bug-free silicon in complex SoCs.
- Strong problem-solving and communication skills, with the ability to collaborate effectively in a team setting.

- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 4 years of experience working with verification methodologies and languages, including SystemVerilog and UVM.
- Experience with interconnect protocols such as AXI, APB, and ACE.
- Experience building and maintaining verification test benches, test cases, and test environments.
## Skills

- Universal Verification Methodology (Uvm)
- Doctor of Philosophy (PhD)
- Debugging
- Interconnect Design
- Computer Architecture
- Test Bench Design
- Associate Certified Entomologist (Ace)
- SystemVerilog
- Problem Solving
- System on Chip (SoC) Design
- Unified Power Format (Upf)
- Formal Verification
- Constrained-Random Verification
- Coverage Closure
- Digital Design
- AXI (Advanced eXtensible Interface)
- Simulations
- Test Planning
- Computer Engineering
- Computer Science
- Design Specifications
- Electrical Engineering
- Communication
- Test Case Design

## How to Apply

[Apply for this position](https://www.foundrole.com/jobs/design-verification-engineer-silicon-at-google-01a0d985-b147-7d4d-b3bd-e995c9180189?utm_source=ai_markdown)

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- [More jobs at Google](https://www.foundrole.com/companies/google?utm_source=ai_markdown)
- [Browse all companies](https://www.foundrole.com/companies?utm_source=ai_markdown)