---
title: 'ASIC Verification Engineer: 26 at Akraya'
description: 'Akraya is hiring for the ASIC Verification Engineer: 26 role in Allentown, PA.
  Pays $70–$72 per hour. See the full description and apply.'
type: job
url: https://www.foundrole.com/jobs/asic-verification-engineer-26-at-akraya-01a16e70-34d2-76aa-90b2-d89fbf3c0479
date: 2026-11-15T01:26:44Z
og_description: 'Join Akraya as ASIC Verification Engineer: 26 in Allentown, PA. Pays $70–$72
  per hour. On-site role. Requires 5+ years of experience.'
og_image: https://www.foundrole.com/og/q3r34l.png
breadcrumbs:
  - label: Home
    url: https://www.foundrole.com/
  - label: Search
    url: https://www.foundrole.com/jobs
---

| | |
|---|---|
| **Company** | Akraya |
| **Location** | Allentown, PA |
| **Salary** | $70/hr - $72/hr |
| **Type** | Contractor |
| **Posted** | Oct 19, 2026 |

## Is this job real?

**Ghost job check:** A- · Low risk. Probably a real opening.

## Visa sponsorship

- **H-1B:** Akraya sponsors H-1B visas. It filed 8 H-1B petitions (FY2026 Q1 – FY2026 Q4).
- **E-Verify:** No E-Verify enrollment on record for Akraya.

## Pay for similar jobs

Most similar jobs pay $99,000 – $143,000 a year (median $137,000).

## Description

Primary kills: System Verilog (Expert), UVM (Expert), ASIC/SoC Verification (Advanced), Verification Testbench (Advanced), RTL/Design Verification (Advanced)  
Contract Type: W2 Only  
Duration: 12 Months  
Location: Allentown, PA (100% Onsite) or Carlsbad, CA (100% onsite)  
Pay Range: $70-$72/hr on W2  

**Job Summary:**  
We are seeking an experienced **ASIC Verification Engineer** with **5–12 years of experience** to support next-generation SoC designs for client's Silicon One team. The ideal candidate will have strong hands-on experience with **SystemVerilog, UVM-based verification, testbench development, and block-to-system-level verification**.  

**Key Responsibilities:**

- Develop and maintain **UVM-based verification environments and testbenches** for ASIC/SoC designs.
- Create verification plans and develop **assertions, agents, traffic generators, scoreboards, and test cases**.
- Perform **SystemVerilog coding, simulation, debug, and failure analysis**.
- Collaborate with design and cross-functional teams to improve design testability and verification coverage.
- Lead complex verification/debug efforts and support **timing, gate-level, and post-silicon bring-up** activities.
 **Must-Have Skills:**

- **5–12 years of ASIC/SoC verification experience** with strong hands-on **SystemVerilog and UVM** expertise.
- Proven experience developing **UVM testbenches, verification plans, and verification infrastructure** from block to system level.
- Experience with **timing/gate-level simulation, complex debug, and C programming for firmware/post-silicon bring-up**.
- Bachelor's/Master's degree in **Electrical Engineering, Computer Engineering, Communications Engineering, or related field**.
 **Industry Experience:**

- Formal verification and automation using **Python or Perl**.
- High-speed protocols such as **PCIe, UCIe**, etc.
- Analog debug, DAC/client calibration, and white-box verification.
- Experience with AI-based CAD/verification efficiency initiatives.

**ABOUT AKRAYA**  
Akraya is an award-winning IT staffing firm consistently recognized for our commitment to **excellence and a thriving work environment**. **Most recently, we were recognized Stevie Employer of the Year 2025, SIA Best Staffing Firm to work for 2025, Inc 5000 Best Workspaces in US (2025 & 2024) and Glassdoor's Best Places to Work (2023 & 2022)!**  

**Industry Leaders in Tech Staffing**  
As Talent solutions provider for Fortune 100 Organizations, Akraya's industry recognitions solidify our leadership position in the IT staffing space. **We don't just connect you with great jobs, we connect you with a workplace that inspires!**  

**Join Akraya Today!**  
Let us lead you to your dream career and experience the Akraya difference. Browse our open positions and join our team!
## Skills

- ASIC Design
- Universal Verification Methodology (Uvm)
- Debugging
- C
- Perl
- Digital-to-Analog Converter (Dac) Design
- Post-Silicon Validation
- PCI Express PCIe
- SystemVerilog
- Testability
- Calibration
- Python
- Automation
- Artificial Intelligence
- Formal Verification
- Analog Circuit Design
- Hardware Bring-up
- Simulations
- Computer-Aided Design
- Computer Engineering
- Electrical Engineering
- Communication
- Verification Plans
- Electrical Machines
- Test Case Design
- SoC Verification
- Firmware

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